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Logic synthesis
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41	On Equivalence Checking and Logic Synthesis of Circuits with a Common Specification Eugene Goldberg Cadence Berkeley Labs 1995, University Ave., suite 460, Berkeley,CA, USA, 94704 tel, email: egold@cadenc Add to Reading List Source URL: eigold.tripod.com Language: English - Date: 2005-03-07 15:13:04
42	Syntax-Guided Synthesis Rajeev ALUR a , Rastislav BODIK b , Eric DALLAL c , Dana FISMAN a , Pranav GARG d , Garvit JUNIWAL b , Hadas KRESS-GAZIT e , P. MADHUSUDAN d , Milo M. K. MARTIN a , Mukund RAGHOTHAMAN a , Shamwadi Add to Reading List Source URL: sygus.seas.upenn.edu Language: English - Date: 2015-01-10 00:32:21 Predicate logic Theoretical computer science Formal methods NP-complete problems First-order logic Satisfiability Modulo Theories Expression Type system Function Mathematics Logic Mathematical logic
43	ISE Design Tool Flow FPGA 1 FPGA16000-ILT (v1.0) Course Specification Add to Reading List Source URL: www.xilinx.com Language: English - Date: 2014-08-29 18:31:31 Xilinx ISE Reconfigurable computing Electronic design automation Hardware description languages Xilinx Logic synthesis Field-programmable gate array VHDL Application-specific integrated circuit Electronic engineering Electronics Digital electronics
44	Vivado Design Suite Tool Flow FPGA 1 FPGA-VDF-ILT (v1.0) Course Specification Add to Reading List Source URL: www.xilinx.com Language: English - Date: 2015-05-21 13:22:32 Reconfigurable computing Hardware description languages Field-programmable gate array Xilinx Logic synthesis VHDL Application-specific integrated circuit Timing closure Electronic engineering Electronics Digital electronics
45	•i. I PROBABILISTIC LOGICS AND THE SYNTHESIS OF RELIABLE ORGANISMS FROM UNRELIABlE COMPONENTS Add to Reading List Source URL: arep.med.harvard.edu Language: English - Date: 2015-03-01 08:45:15 Logic Propositional calculus Automaton Quantum dot cellular automaton Automata theory Theory of computation Mathematical logic
46	Designing with VHDL FPGA 1 LANG11000-ILT (v1.0) Course Specification Add to Reading List Source URL: www.xilinx.com Language: English - Date: 2014-11-12 18:34:24 VHDL Digital electronics Field-programmable gate array Logic synthesis Xilinx Register-transfer level Electronic engineering Hardware description languages Electronic design automation
47	Specification-Guided Controller Synthesis for Linear ∗ Systems and Safe Linear-Time Temporal Logic Matthias Rungger Manuel Mazo Jr. Add to Reading List Source URL: www.mmazojr.net Language: English - Date: 2014-09-01 07:12:16
48	The additional difficulties for the automatic synthesis of specifications posed by logic features in functional-logic languages∗ Giovanni Bacci1 , Marco Comini1 , Marco A. Feliú2 , and Alicia Villanueva2 1 Add to Reading List Source URL: people.cs.aau.dk Language: English - Date: 2013-03-04 02:22:36
49	CyberWorkBench® High-Level Synthesis and Verification by: SystemC High-Level Synthesis and Verification Add to Reading List Source URL: www.aldec.com Language: English - Date: 2013-08-07 16:44:00 Fabless semiconductor companies Hardware description languages Logic design Aldec Field-programmable gate array Xilinx High-level synthesis Altera SystemC Electronic engineering Digital electronics Electronic design automation
50	Mining Apps to Learn Normal Behavior Add to Reading List Source URL: www.informatics-europe.org Language: English - Date: 2014-10-21 03:47:57 Formal methods Logic in computer science SQL Postcondition Specification language Formal specification XML Program synthesis Computing Theoretical computer science Software engineering

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